Functional and reliability testing of integrated circuits, particularly very large scale integrated circuits (VLSI), has long been an important aspect of the electronics industry and is becoming ever more important. Presently, chip manufacturers use various testing procedures to determine the effectiveness of their manufacturing processes (i.e., chip yield) and the viability of their circuit designs. Chip users, particularly computer manufacturers, also subject the microcircuits they purchase to reliability testing in order to evaluate the quality of the parts they receive and to insure the quality of their own finished product.
The ideal standard for reliability testing is to subject 100% of the integrated circuits produced to the most rigorous and effective tests that can be devised. In reality, however, the ideal standard is difficult to attain. This is a function of the very large number of integrated circuits currently produced, the time it would take to test all of the chips, and the cost of testing each chip, particularly high density integrated circuits, which may have tens of thousands of gates on each chip. Because 100% testing is too time consuming and prohibitively expensive, many chip manufacturers rely on sample testing in order to evaluate the performance and reliability of a given lot of integrated circuits.
Lot sample testing is unacceptable for certain types of chips, however. Dynamic random access memories (DRAMs), for example, must be subjected to 100% testing of all memory locations in order to ensure that each address is able to store data. Furthermore, some rigorous level of testing must be performed on most random access memory (RAM) chips by the computer manufacturers before installation in computers in order to minimize the effects of infant mortality on the computer manufacturing process. Thorough testing is also typically needed on application specific integrated circuits (ASICs). ASICs are semi-customized chips designed to perform very specific function required by the designer. ASIC chips are usually produced in relatively low volume and at relatively high cost per chip. The operating parameters of ASIC chips are therefore generally not as well known by the end user or as well-documented and reliable as the operating parameters of mass production chips. The ASIC user must generally rely on sparse data sheets provided in the ASIC manufacturer's specifications.
The different methods of reliability testing of integrated circuits include:
1) visual inspection;
2) I.sub.ddq testing--measuring the quiescent (DC) power supply current to determine power dissipation of the IC for a given set of input voltages (or test vectors);
3) burn-in testing--operating the chip for an extended period of time at a high temperature in order to "age" the chip rapidly. This is designed to weed out those chips which are in the infant mortality group before they are sold to the end users;
4) temperature cycling--operating the chip while the temperature is cycled from high temperature to very low temperature and back to high temperature in order to evaluate its performance in real-world conditions;
5) functional testing--application of test vector stimuli and reading the output logic levels (digital "zeroes" and "ones" to verify correct logic operation);
6) parametric testing--application of test vectors to determine precise voltages, currents, switching time, and/or propagation delays.
As noted briefly above, due to their expense, the majority of these tests are performed only on samples of a given lot of microcircuits, thereby reducing reliability of the results. This is especially true of mass produced chips where competition minimizes profit margins. More thorough testing of all or most of the microcircuits in a given lot is then usually reserved for RAM chips and special customers, such as NASA and the military.
The reliability of present methods of testing are also limited in their ability to detect certain kinds of faults. Traditional techniques of testing are generally vendor designed and rely on pass/fail criteria set forth in the vendors own specifications. These tests are generally simple and often fail to identify reliability faults including shorts, open circuits or other abnormalities.
There is therefore a need for circuits, systems and methods which can quickly and consistently identify faults in microcircuits, including potential hazards or latencies that are difficult to detect by traditional means and which may not become apparent until much later.
There is a still further need for circuits, systems and methods which can evaluate the reliability of integrated circuits independently from the specifications and data sheets provided by the vendor of the microcircuits.
There is a still further need for systems and methods which thoroughly and rapidly test the performance of very high-density integrated circuits, such as CMOS DRAMs, ASICs, microprocessors and related peripheral chips.